THE REFERENCE LIBRARY

Ideas from the field

Conference papers, tutorials, and presentations authored or co-authored by Stuart Sutherland.

2016 · PAPER / PRESENTATION

Adopting the SystemsVerilog Universal Verification Methodology (UVM)

DVClub Portland OR - Design Verification Club:
Adopting the SystemsVerilog Universal Verification Methodology (UVM)
by Stuart Sutherland
presentation slides

presentation slides ↗

2015 · PAPER / PRESENTATION

Who Put Assertions In My RTL Code? And Why?

SNUG Silicon Valley - Synopsys Users Group Conference:
Who Put Assertions In My RTL Code? And Why?
by Stuart Sutherland
(Awarded Best Paper Presentation, First Place)
paper | presentation slides

Ideas from the field

Adopting the SystemsVerilog Universal Verification Methodology (UVM)

Who Put Assertions In My RTL Code? And Why?

UVM Rapid Adoption: A Practical Subset of UVM

SystemsVerilog Assertions Tutorial and Assertions Planning?

Can My Synthesis Compiler Do That? What ASIC and FPGA Synthesis Compilers support in SystemVerilog-2012

Can My Synthesis Compiler Do That?

I'm Still In Love With My X (advantages and hazards of X propagation in simulation)

Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification

What's New in SystemVerilog-2012

What, If Anything, In SystemVerilog Will Help Me With FPGA-based Design?

Summary of What is New in SystemVerilog-2012

Adding Last-Minute Assertions: Lessons Learned (a little late) about Designing for Verification

Is SystemVerilog Useful for FPGA Design? (" Burn-and-Learn" versus " Learn-and-Burn")

SystemVerilog Is Getting Even Better! An Update on the Proposed SystemVerilog-2009 Standard

Push Button Engineering and Top Ten Reasons Engineers Use SystemVerilog

Verilog Is Not Called Verilog Anymore! The Merging of the Verilog and SystemVerilog IEEE Standards

More Standard Gotchas: Subtleties in Verilog and SystemVerilog That Every Engineer Should Know

Getting Started with SystemVerilog Assertions

A Proposal for a Standard Synthesizable SystemVerilog Subset

SystemVerilog Assertions Are For Design Engineers, Too!

Modeling with SystemVerilog in a Synopsys Synthesis Design Flow

Standard Gotchas: Subtleties in Verilog and SystemVerilog That Every Engineer Should Know

SystemVerilog Interoperability Checklist

SystemVerilog Saves the Day--the Evil Twins are Defeated! unique and priority are the new Heroes

SystemVerilog is for Everyone (not just system designers)

SystemVerilog, ModelSim and You

The Verilog PLI is Dead (maybe) -- Long Live the the SystemVerilog DPI!

Integrating SystemC Models Into Verilog Using the SystemVerilog DPI

SystemVerilog Adoption Plan

Modeling FIFO Communication Channels Using SystemVerilog Interfaces

HDVL += (HDL & HVL) SystemVerilog 3.1: The Hardware Description AND Verification Language

SystemVerilog 3.1: It's What the DAVEs In Your Company Asked For

Overview of SystemVerilog 3.1

Using Verilog-2001 for Design Verification

Using PLI 2.0 (VPI) with VCS

Verilog, The Next Generation: Accellera's SystemVerilog

Getting the most from Verilog-2001

Using Verilog-2001 for Modeling Hardware

What's New in the IEEE 1364 Verilog-2001 Standard

IEEE 1364 Verilog PLI Standards Group Report

Using the PLI VPI Library

IEEE 1364 Verilog PLI Standards Group Report

Will Cadence Miss the Boat?

Switching to the New PLI Standard

IEEE 1364 Verilog PLI Standards Group Report

Understanding Nonblocking Assignments

The IEEE 1364-1995 Verilog PLI Standard

Modeling for best simulation performance