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RTL Modeling with SystemVerilog For Simulation and Synthesis:
Using SystemVerilog for ASIC and FPGA Design>

by Stuart Sutherland
Paperback, 488 pages, $120 US retail price
Copyright 2017, Sutherland HDL, Inc., Tualatin, Oregon
ISBN: 978-1-5467-7634-5

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly.

Download book examples (ZIP file)

This "RTL Modeling with SystemVerilog for Simulation and Synthesis" book was written as a companion to the book "SystemVerilog for Verification" by Chris Spear, also published by Springer. As the titles indicate, each book covers a different sphere of SystemVerilog; the former on the design modeling constructs and the latter on the design verification constructs.

Verilog and SystemVerilog Gotchas:
101 Common Coding Error and How to Avoid Them

by Stuart Sutherland and Don Mills
Hardcover, 218 pages, $99 US retail price
Copyright 2006, Springer (formerly Kluwer), Norwell MA
ISBN: 978-0-387-71714-2
Publisher's web page

This book has a mistake on almost every page! On purpose. The book shows common coding mistakes that the authors or others have made in their Verilog or SystemVerilog code. Often these mistakes looked like perfectly reasonable code, but cause functional errors in simulation or synthesis that were difficult to debug. And that's the definition of a Gotcha -- code that looks correct, but which behaves differently than expected. (The examples in this book are not available for download, but they are very short and easy to type in.)

SystemVerilog For Design:
A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition>

by Stuart Sutherland (primary author), Simon Davidman, and Peter Flake
Hardcover, 418 pages, $189 US retail price
Copyright 2006, Springer (formerly Kluwer), Norwell MA
ISBN: 978-0-387-33399-1
Publisher's web page

SystemVerilog provides a rich set of enhancements to the older IEEE 1364-2005 Verilog Hardware Description Language. This book examines the synthesizable portion of those extensions, which are extensive and important for RTL designers to take advantage of. This book does not cover the full, traditional Verilog HDL -- this book for engineers who already know Verilog, and need to understand what SystemVerilog adds to Verilog, specific for modeling at the RTL level. The focus of the book is how to properly use the SystemVerilog extensions to Verilog to write models that both simulate and synthesize correctly. This second edition reflects the official IEEE 1800-2005 SystemVerilog standard. The SystemVerilog extensions described in this book include:
• Packages and the $unit declaration space
• Modeling with new 2-state data types
• Representing complex data with structures, unions and arrays
• Using user-defined data types and enumerated data types
• Proper usage of new synthesizable procedural blocks
• Working with enhanced procedural programming statements and operators
• Simplifying design hierarchy using interfaces and new netlist shortcuts
• Using SystemVerilog for abstract, transaction level modeling

(The example show in this second edition examples are not available for download due to copyright limitations. Most of the examples are also in the first edition, which are available for download. Download the first edition examples (UNIX tar file) and first edition errata (text file).

This "SystemVerilog for Design" book was written as a companion to the book "SystemVerilog for Verification" by Chris Spear, also published by Springer. As the titles indicate, each book covers a different sphere of SystemVerilog; the former on the design modeling constructs and the latter on the design verification constructs.

Verilog-2001:
A Guide to the New Features in the Verilog Hardware Description Language

by Stuart Sutherland
Hardcover, 148 pages, $99 US retail price
Copyright 2002, Springer (formerly Kluwer), Norwell MA
ISBN: 978-0-7923-7568-5
Publisher's web page

The IEEE 1364-2001 standard, nicknamed "Verilog-2001", is the first major update to the Verilog language since its inception in 1984. This book presents 45 significant enhancements contained in Verilog-2001 standard. A few of the new features described in this book are:
• ANSI C style port declarations for modules, primitives, tasks and functions
• Automatic tasks and functions (re-entrant tasks and recursive functions)
• Multidimensional arrays of any data type, plus array bit and part selects
• Signed arithmetic extensions, including signed data types and sign casting
• Enhanced file I/O capabilities, such as $fscanf, $fread and much more
• Enhanced deep submicron timing accuracy and glitch detection
• Generate blocks for creating multiple instances of modules and procedures
• Configurations for true source file management within the Verilog language

This book assumes that the reader is already familiar with using Verilog. It supplements other excellent books on how to use the Verilog language.

The Verilog PLI Handbook:
A Tutorial and Reference Manual on the Verilog Programming Language Interface, Second Edition

by Stuart Sutherland
Hardcover, 808 pages, $160 US retail price
Copyright 2002, Springer (formerly Kluwer), Norwell MA
ISBN: 978-0-7923-7658-3
Publisher's web page

The Verilog PLI provides a means to customize a Verilog simulator to perform virtually any engineering task desired, such as adding custom design debug utilities to a simulator, adding proprietary file read/write utilities to a simulator, interfacing C language models to a simulator, etc. The PLI Handbook serves as both a user's guide for learning how to use the Verilog PLI, and as a comprehensive reference manual on the Verilog PLI standard. There are two major generations of the Verilog PLI: the TF/ACC generation (sometimes called "PLI 1.0") and the VPI generation (sometimes called "PLI 2.0"). Both generations are included in the IEEE 1364 Verilog standard. This book provides equal and detailed coverage of both the TF/ACC and the VPI generations of the PLI.

"This book brings clarity to the Verilog Programming Language Interface. The descriptions and examples shed new light on aspects of the PLI that had previously been murky. Stuart Sutherland has produced the definitive guide to all versions of the PLI. I highly recommend this book to all Verilog users who want to learn the PLI." Chris Spear, Verification Consultant, Synopsys, Inc.

Download PLI book examples (UNIX tar file)

Note: The SystemVerilog standard has added extensions to the VPI libraries that are not reflected in this book. SystemVerilog has also added a third programming interface called the Direct Programming Interface (DPI), which is also not covered in this book.

Verilog HDL Quick Reference Guide, based on the Verilog-2001 Standard

by Stuart Sutherland
Softcover, 50 pages, $14.95 US retail price
Copyright 2001, Sutherland HDL, Inc., Tualatin, OR
ISBN: 1-930368-03-8

A handy and concise quick reference guide covering the syntax of the complete Verilog language. Updated to include the dozens of new enhancements in the IEEE 1364-2001 Verilog standard, such as generates, multi-dimensional arrays, C style port declarations and signed arithmetic. Professionally printed and spiral bound, this popular reference guide makes it easy and fast to look up Verilog keywords and syntax. The guide is fully indexed and includes many examples which illustrate the Verilog language in context.

Note:This book is no longer available for purchase, but is provided as part of the training materials in Sutherland HDL's "Verilog and SystemVerilog Language Primer" and "Verilog/SystemVerilog for Design and Synthesis" workshops.

Downloadable PDF Version

A PDF version of this Quick Reference Guide is available for free download. Permission is granted by Sutherland HDL to download and/or print copies of this reference guide for personal use only. The reference guide cannot be used for commercial purposes or distributed in any form or by any means without obtaining express permission from Sutherland HDL.

Verilog-2001 Quick Reference as a PDF document