For design & verification engineers
Practical Verilog, SystemVerilog, UVM, and assertion-based verification training. Learn directly from experienced engineers, with hands-on labs and techniques you can put to work.
BUILD YOUR EXPERTISE
Verilog/SystemVerilog for Design and Synthesis is a comprehensive workshop covering the complete Verilog Hardware Description Language and the synthesizable portions of SystemVerilog, including user-defined types, enumerated types, structures, and self-verifying decision statements.
Getting the most benefit from advanced verification methodologies such as UVM, OVM and VMM requires understanding the SystemVerilog constructs on which these methodologies are built.
The Universal Verification Methodology (UVM) standard defines an industry-wide consistent way of using SystemVerilog for the verification of complex designs.
SystemVerilog Assertions for Design and Verification Engineers is an advanced workshop covering the IEEE 1800 SystemVerilog Assertions (SVA).
KNOWLEDGE THAT GOES TO WORK
Go beyond syntax with practical workshops developed and presented by experienced design and verification engineers.
Meet Sutherland HDL ↗Hands-on labs reinforce the concepts and connect them to real design challenges.
Choose a live online workshop or bring private training to your organization.
Continue learning with course materials, books, papers, and reference guides.
CLASS SCHEDULE
| Class | Dates and times | Region | Price | Registration |
|---|---|---|---|---|
| Verilog/SystemVerilog for Design and Synthesis (SVD) Live online | Dec 7, 2026 – Dec 12, 2026
| India | $1,000 | Register → |
| Verilog/SystemVerilog for Design and Synthesis (SVD) Live online | Dec 7, 2026 – Dec 11, 2026
| North America West | $1,000 | Register → |
| SystemVerilog Object Oriented Verification (SVV) Live online | Dec 14, 2026 – Dec 18, 2026
| India | $1,000 | Register → |
| SystemVerilog Object Oriented Verification (SVV) Live online | Dec 14, 2026 – Dec 18, 2026 8:00 AM PST – 3:00 PM PST | North America West | $1,000 | Register → |
| Verilog/SystemVerilog for Design and Synthesis (SVD) Live online | Jan 11, 2027 – Jan 15, 2027 12:00 PM GMT+1 – 4:00 PM GMT+1 | Europe | $1,000 | Register → |
FROM THE BOOKSHELF
Explore Stuart Sutherland’s books and reference guides.
Explore the library ↗
