Overview

Getting the most benefit from advanced verification methodologies such as UVM, OVM and VMM requires understanding the SystemVerilog constructs on which these methodologies are built. SystemVerilog Object-Oriented Verification provides that knowledge. Concepts presented include special testbench modeling constructs, clocking domains, writing Object Oriented testbenches, constrained random verification, coverage, an overview of SystemVerilog assertions, and an overview of the SystemVerilog Universal Verification Methodology (UVM). Engineers learn how to utilize object inheritance and polymorphism, mailboxes, semaphores, specifying randomization constraints, specifying functional coverage, and dynamic arrays. The workshop also covers best-practices for using SystemVerilog programming and operator constructs in verification, including how to properly use blocking and nonblocking assignments. Labs reinforce the concepts learned, with forty percent of the class time devoted to hands-on experience.

Available Formats and Course Lengths

This workshop is available in two configurations:

• As a stand-alone workshop for engineers who are already familiar with Verilog or SystemVerilog.
  •  Instructor-led onsite private workshop: 4-days
  •  Instructor-led eTutored™ live online workshop: 5-days
  •  Instructor-mentored eTutored™ self-paced online workshop: 2 to 30 days
• Combined with Sutherland HDL's "Verilog and SystemVerilog Foundations" workhsop for engineers who have not had formal training or substantial experience with Verilog or SystemVerilog.
  •  Instructor-led onsite private workshop: 5-days
  •  Instructor-led eTutored™ live online workshop: 5-days
  •  Instructor-mentored eTutored™ self-paced online workshop: 2 to 30 days

Intended Audience and Objectives

This workshop is for design and/or verification engineers who will be creating test environments for the verification of digital designs. At the conclusion of this workshop, engineers will understand how to take full advantage of the verification capabilities in the SystemVerilog language, in order to develop object-oriented testbenches that utilize constrained-random verification methodologies, functional coverage, mailboxes and scoreboarding. This workshop, or equivalent knowledge, is a mandatory prerequisite for Sutherland HDL's "Mastering SystemVerilog UVM" workshop.

Prerequisite Knowledge (essential)

Attendees must have a working knowledge of the Verilog and/or SystemVerilog language. The course materials, lecture, and labs utilize the SystemVerilog programming constructs, with the assumption that these constructs are familiar. This familiarity can come from prior experience with Verilog and/or SystemVerilog, or by completing Sutherland HDL's "Verilog and SystemVerilog Language Foundations" workshop.

Included Materials

• Full-color training binder with lecture slides, lab instructions, and supplemental information. (eTutored™ self-paced courses receive an eBook instead of a binder.)
• Lab files, including example solutions that illustrate proper and efficient coding styles.

Customized Training

At times, your engineering team may require unique training to meet the needs of your specific projects.  Sutherland HDL can customize our standard workshops to meet those needs, when presented as a private onsite or online workshop.  request info