Overview

SystemVerilog Assertions for Design and Verification Engineers is an advanced workshop covering the IEEE 1800 SystemVerilog Assertions (SVA). SVA enables engineers to verify extremely complex logic, using a concise, portable methodology. SystemVerilog Assertions offer improvements at every stage of design and verification process. This workshop provides a thorough examination of SVA and assertion-based verification methodologies. Both immediate and concurrent assertions are presented, with discussion on the appropriate usage of each type of assertion. SVA sequence and property blocks are covered in great detail, with a focus on the semantics and proper usage of the many sequence and property operators. The presentation materials are filled with practical examples of writing assertions for various types of hardware logic. Topics presented in this comprehensive study on SVA include property and sequence arguments, multiple thread termination and uniqueness, assertion-based system functions, and clock domain crossing. Several labs reinforce the principles presented, with forty percent of the class time devoted to hands-on experience.

Available Formats and Course Lengths

This workshop is available in two configurations:

• As a stand-alone workshop for engineers who are already familiar with Verilog or SystemVerilog.
  •  Instructor-led onsite private workshop: 2-days
  •  Instructor-led eTutored™ live online workshop: 3-days
  •  Instructor-mentored eTutored™ self-paced online workshop: 2 to 30 days
• Combined with Sutherland HDL's "Verilog and SystemVerilog Foundations" workhsop for engineers who have not had formal training or substantial experience with Verilog or SystemVerilog.
  •  Instructor-led onsite private workshop: 3-days
  •  Instructor-led eTutored™ live online workshop: 4-days
  •  Instructor-mentored eTutored™ self-paced online workshop: 2 to 30 days

Intended Audience and Objectives

This workshop is for both digital design engineers and digital verification engineers. Design engineers will learn how to place simple assertions directly in RTL code to trap logic X values and to validate assumptions made in the RTL code (such as validating that a 1-hot state machine always has 1-hot values). Verification engineers will immediately be productive with assertion-based verification methodologies and know how to write assertions and sequences that describe and verify complex design functionality.

Prerequisite Knowledge (essential)

Attendees must have a working knowledge of the Verilog and/or SystemVerilog language. The course materials, lecture, and labs utilize the SystemVerilog programming constructs, with the assumption that these constructs are familiar. This familiarity can come from prior experience with Verilog and/or SystemVerilog, or by completing Sutherland HDL's "Verilog and SystemVerilog Language Foundations".

Included Materials

• Full-color training binder with lecture slides, lab instructions, and supplemental information. (eTutored™ self-paced courses receive an eBook instead of a binder.)
• Lab files, including example solutions that illustrate proper and efficient coding styles.

Customized Training

At times, your engineering team may require unique training to meet the needs of your specific projects.  Sutherland HDL can customize our standard workshops to meet those needs, when presented as a private onsite or online workshop.  request info