Precision RTL Synthesis 2013a.9 (Production Release) Thu Aug 8 04:05:44 PDT 2013

Copyright (c) Mentor Graphics Corporation, 1996-2013, All Rights Reserved.
Portions copyright 1991-2008 Compuware Corporation
UNPUBLISHED, LICENSED SOFTWARE.
CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS

Running on Windows 7 stuart@SHDL-1 Service Pack 1 6.01.7601 x86

Start time Sat Feb 08 01:13:58 2014

Table of Contents

  1. Section-1: Hardware
  2. Section-2: Operating_System
  3. Section-3: Precision_Settings

 

Section-1: Hardware

Processor

Processor(s): 1 Processor(s) Installed.
   [01]: Intel64 Family 6 Model 58 Stepping 9 GenuineIntel ~2001 Mhz

Memory

Total Physical Memory: 7,889 MB
Available Physical Memory: 3,350 MB
Virtual Memory: Max Size: 15,776 MB
Virtual Memory: Avaliable: 11,026 MB
Virtual Memory: In Use: 4,750 MB

 

Section-2: Operating_System

OS Name: Windows 7
OS Version: 6.1.7601 Service Pack 1 Build 7601
Hotfix(s): 155 Hotfix(s) Installed.
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Section-3: Precision_Settings



## Technology Settings
setup_design -manufacturer Xilinx -family VIRTEX -part v50bg256 -speed 6


## Input File Settings
set_input_dir D:/sandbox/book_examples/chapter-05/synplify
add_input_file -format SystemVerilog -work work {../../../dvcon_paper_examples/exmp16c.sv}


## Output File Settings
setup_design -basename="my_chip"


## Design Settings
setup_design -addio
setup_design -addio_unused=false
setup_design -vhdl=false
setup_design -verilog
setup_design -edif=false
setup_design -vqm=false
setup_design -vendor_constraint_file=false
setup_design -transformations=false
setup_design -retiming=false
setup_design -altera_dsp_retiming=false
setup_design -pa_io_pin_location
setup_design -advanced_fsm_optimization=false
setup_design -compile_for_area=false
setup_design -compile_for_timing=false
setup_design -safe_fsm_type="none"
setup_design -encoding="onehot"
setup_design -resource_sharing
setup_design -array_bounds_check=false
setup_design -preserve_user_encoding=false
setup_design -transform_tristates="auto"
setup_design -process_tristates=false
setup_design -edif_bus_extraction_style="%s(%d:%d)"
setup_design -black_box_flow=false
setup_design -bottom_up_flow=false
setup_design -white_box_flow
setup_design -retain_inouts
setup_design -frequency=""
setup_design -radhardmethod="none"
setup_design -input_delay=""
setup_design -output_delay=""
setup_design -boundary_opt
setup_design -partition_size="80000"
setup_design -global_clock_limit=""
setup_design -infer_gsr
setup_design -infer_muxed_arith_operators
setup_design -clearbox=false
setup_design -search_path {}
setup_design -libext=""
setup_design -y {}
setup_design -mem_init_path {}
setup_design -altera_mangle_prefix="_MGC"
setup_design -2004c_compile_mode=false
setup_design -enable_synthoff_regions=false
setup_design -overrides {}
setup_design -hdl { systemverilog2009 vhdl_2002 }
setup_design -defines {}
setup_design -automap_work=false
setup_design -error_design_contention=false
setup_design -all_file_cunit_scope=false
setup_design -sv31acompat=false
setup_design -vcs_compat=false
setup_design -compile_udps=false
setup_design -relaxed_compile=false
setup_design -vendor_override_lib="xilinx"
setup_design -max_loop_count=5000
setup_design -ignore_ram_rw_collision=false
setup_design -altera_netlist_opt=false
set_path_compression_options -run_during_physical_synthesis=false
setup_design -sta_time_resolution=-12
setup_design -gated_clock=0
setup_design -auto_save_placement
setup_design -auto_resource_allocation_ram=false
setup_design -enable_incr_synth=false
setup_design -enable_incr_pnr=false
setup_design -dsp_across_hier=false
setup_design -extensive_dsp_drc
setup_design -relax_dsp_drc=false
setup_design -flatten_small_rtl_modules=false
setup_design -timequest_sdc
setup_design -reencode_fsm_outputs
setup_design -dont_pass_synthesis_define=false
setup_design -max_fanout=10000
setup_design -pa_max_fanout=10000
setup_design -max_fanout_strategy="AUTO"
setup_design -compile_initial_values=false
setup_design -block_ram_cutoff=0
setup_design -block_rom_cutoff=0
setup_design -infer_ram
setup_design -infer_rom
setup_design -control_set_optimize=false
setup_design -control_set_threshold=6
setup_design -modgen="auto"
setup_design -modgen_mode="auto"
setup_design -lut_combine="auto"
setup_design -fv_flow="none"
setup_design -enable_force_distributed_ram=false
setup_design -enable_merge_equal_op_b4_modgen_resolve=false
setup_design -gate_level_opt=false
setup_design -assured_synthesis=false
setup_design -flatten_small_blocks
setup_design -write_verilog_escape_names
setup_design -use_dffenable
setup_design -compatibility_mode="none"
setup_design -preserve_instantiated_cells=false
setup_design -ignore_utilization=false


## Place and Route Settings for Flow 'ISE 5.1' Command 'Integrated Place and Route'
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -install_dir {$XILINX}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -no_exec {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -smartguide {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -smartguide_file {"*.ncd \"\""}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -optimization_control {std}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -global_opt {off}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -disable_logic_replication {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -do_not_remove_unused_logic {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -ignore_keep_hierarchy {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -par_ol {high}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -ba_format {None}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -exe_mode {Auto}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -timing_paths_per_constraint {10}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -bits {0}


## Place and Route Settings for Flow 'ISE 5.1' Command 'Generate Vendor Constraint File'
setup_place_and_route -flow "ISE 5.1" -command "Generate Vendor Constraint File" -enable_auto_offset_relaxation {0}
setup_place_and_route -flow "ISE 5.1" -command "Generate Vendor Constraint File" -use_ucf_timing_constraints {False}
setup_place_and_route -flow "ISE 5.1" -command "Generate Vendor Constraint File" -no_exec {0}


## Place and Route Settings for Flow 'ISE 5.1' Command 'Advanced Options'
setup_place_and_route -flow "ISE 5.1" -command "Advanced Options" -use_pnr_script_cl {0}
setup_place_and_route -flow "ISE 5.1" -command "Advanced Options" -pnr_script_cl {user_pnr_script.tcl}


## Place and Route Settings for Flow 'ISE' Command 'Integrated Place and Route'
setup_place_and_route -flow ISE -command "Integrated Place and Route" -install_dir {$XILINX}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -no_exec {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -smartguide {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -smartguide_file {"*.ncd \"\""}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -optimization_control {std}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -global_opt {off}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -disable_logic_replication {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -do_not_remove_unused_logic {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -ignore_keep_hierarchy {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -par_ol {high}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -ba_format {None}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -exe_mode {Auto}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -timing_paths_per_constraint {10}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -bits {0}


## Place and Route Settings for Flow 'ISE' Command 'Generate Vendor Constraint File'
setup_place_and_route -flow ISE -command "Generate Vendor Constraint File" -enable_auto_offset_relaxation {0}
setup_place_and_route -flow ISE -command "Generate Vendor Constraint File" -use_ucf_timing_constraints {False}
setup_place_and_route -flow ISE -command "Generate Vendor Constraint File" -no_exec {0}


## Place and Route Settings for Flow 'ISE' Command 'Advanced Options'
setup_place_and_route -flow ISE -command "Advanced Options" -use_pnr_script_cl {0}
setup_place_and_route -flow ISE -command "Advanced Options" -pnr_script_cl {user_pnr_script.tcl}


## Current Place and Route Flow
setup_place_and_route -flow ISE
setup_analysis -clock_frequency
setup_analysis -summary
setup_analysis -num_summary_paths=10
setup_analysis -critical_paths
setup_analysis -num_critical_paths=1
setup_analysis -timing_violations
setup_analysis -net_fanout
setup_analysis -clock_domain_crossing=false
setup_analysis -missing_constraints=false