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Sutherland HDL provides expert training workshops on Verilog and SystemVerilog.

 

 

 

Sutherland HDL training workshops help engineers become true Verilog and SystemVerilog wizards! Workshops are developed and presented by engineering experts with many years of experience in design and verification. Sutherland HDL has trained thousands of engineers throughout the United States, and in Canada, England, Germany, Japan, Malaysia, and Hong Kong.
 

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Stuart Sutherland, founder of Sutherland HDL, is a recognized Verilog and SystemVerilog expert, with more than 23 years of experience with Verilog and SystemVerilog. He is an active member of the IEEE Verilog and SystemVerilog standards group. He is also been a technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals since the standards began. Mr. Sutherland has authored several popular books and conference papers on Verilog and SystemVerilog.

Stuart Sutherland holds a Bachelors Degree in Computer Science with an emphasis in Electronic Engineering Technology and a Masters Degree in Education with an emphasis on eLearning online course development.

 

Verilog and SystemVerilog Quiz and Tips

This Verilog quiz illustrates a real problem encountered when writing synthesis test cases for the DVCon-2014 conference (March 3-6, 2014). The paper is "Can My Synthesis Compiler Do That?" by Stu Sutherland and Don Mills. The paper shows how using SystemVerilog for ASIC and FPGA design can simplify code and reduce the risk of coding errors.

The example below illustrates passing an array of data through a module port. This is not easy to do in Verilog, and the authors made the simple coding mistake shown in the code below. Considerable time was lost debugging the error. Can you find the mistake?

This test case from the paper is about how Verilog does not allow arrays to be passed through module ports. A port can only be a vector that is 1 or more bits wide. This Verilog limitation means that to pass an array through a port requires first "packing" the array into a vector that can represent the entire array. Loops are often used to pack the array by iterating through each element of the array and assiging the value of each element into a part-select of the large vector. Conversely, to receive an array as an input also requires the array values having been packed into a single vector, which must the module then unpack and loaded the input array. The packing and unpacking algorithms are an easy place to make a coding error that can be difficult to find.

In this example, a 2-dimensional array representing a frame of red, green and blue (RGB) color values needs to be passed out of a module. The array is a 16x3 2-dimensional array of 8-bit values. The port size for passing this array needs to be 384 bits wide (16x3x8 = 384). Nested loops are used to assign each element of the RGB frame array to the correct part-select of the 384-bit output port.

NOTE: Only the output array-to-vector packing code is shown--that is where the bug is.

module rgb_frame_array
(input  wire [7:0]  red, green, blue,
 input  wire        clk, rstN,
 output reg         frame_ready,
 output reg [383:0] rgb_frame_out
);
  // internal 16x3 2-D array to store an RGB frame
  reg [7:0] frame_array [0:15][0:2];

  // internal temporary variables
  integer   i, j;

  // INTERNAL LOGIC OF THIS MODULE THAT CALCULATES AN RGB
  // FRAME AND STORES THE FRAME IN THE ARRAY IS NOT SHOWN

  // pack internal frame_array into output port vector
  always @(*) begin
    if (frame_ready) begin
      for (i=0; i<=15; i=i+1) begin
        for (j=0; j<=2; j=j+1) begin
          rgb_frame_out[383-(i*24-(j*8))-:8] = frame_array[i][j];
        end
      end
    end
  end
endmodule //rgb_frame_array

The following outputs are based on the internal array of the model having the RGB valeus of red=1, green=2, blue=3 in all addresses of the array.

EXPECTED OUTPUTS AFTER PASSING ARRAY THROUGH THE PORT:

Address  0: red=1 green=2 blue=3
Address  1: red=1 green=2 blue=3
Address  2: red=1 green=2 blue=3
Address  3: red=1 green=2 blue=3
Address  4: red=1 green=2 blue=3
Address  5: red=1 green=2 blue=3
Address  6: red=1 green=2 blue=3
Address  7: red=1 green=2 blue=3
Address  8: red=1 green=2 blue=3
Address  9: red=1 green=2 blue=3
Address 10: red=1 green=2 blue=3
Address 11: red=1 green=2 blue=3
Address 12: red=1 green=2 blue=3
Address 13: red=1 green=2 blue=3
Address 14: red=1 green=2 blue=3
Address 15: red=1 green=2 blue=3

ACTUAL OUTPUTS AFTER PASSING ARRAY THROUGH THE PORT:

Address  0: red=1 green=3 blue=2
Address  1: red=1 green=3 blue=2
Address  2: red=1 green=3 blue=2
Address  3: red=1 green=3 blue=2
Address  4: red=1 green=3 blue=2
Address  5: red=1 green=3 blue=2
Address  6: red=1 green=3 blue=2
Address  7: red=1 green=3 blue=2
Address  8: red=1 green=3 blue=2
Address  9: red=1 green=3 blue=2
Address 10: red=1 green=3 blue=2
Address 11: red=1 green=3 blue=2
Address 12: red=1 green=3 blue=2
Address 13: red=1 green=3 blue=2
Address 14: red=1 green=3 blue=2
Address 15: red=1 green=x blue=x

Why are the values of green and blue reversed for addresses 0 to 14, and unknown for address 15?

See the answer

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