Training Workshop:
Verilog/SystemVerilog for Design and Synthesis


Verilog/SystemVerilog for Design and Synthesis is a comprehensive workshop covering the complete Verilog Hardware Description Language and the synthesizable portions of SystemVerilog, including user-defined types, enumerated types, structures, and self-verifying decision statements. The workshop integrates in topics from "Verilog and SystemVerilog Language Foundations" and adds detailed discussion and labs on best coding practices for writing synthesizable RTL models that work correctly in both simulation and synthesis. Special attention is given to language subtleties, such as how blocking and non-blocking assignments, programming statements and operators affect simulation and synthesis. About forty percent of the course is devoted to hands-on experience in labs that reinforce the principles presented, including a 5-hour final project modeling a small Digital Signal Processor (DSP).

Available Formats and Course Lengths

•  Instructor-led onsite private workshop: 4-days
•  Instructor-led eTutored™ live online workshop: 5-days
•  Instructor-mentored eTutored™ self-paced online workshop: 2 to 30 days

Intended Audience and Objectives

This workshop is for digital engineers who will be designing with Verilog and SystemVerilog. Students will be immediately productive with using Verilog and SystemVerilog for modeling, simulation and synthesis. Both new Verilog/SystemVerilog users, as well as those who are familiar with Verilog/SystemVerilog and desire a more in-depth knowledge of the language, will benefit from this course.

Prerequisite Knowledge (essential)

Attendees must have a background in digital hardware design engineering. The course materials, lecture, and labs refer to -- but do not define -- digital hardware concepts such as flip-flops, shift-registers, multiplexers, arithmetic logic units, and finite state machines. Familiarity with these digital engineering concepts is critical for understanding and benefiting from this workshop. It is not necessary to already be familiar with the Verilog HDL. This workshop integrates in the topics from Sutherland HDL's "Verilog and SystemVerilog Language Foundations" workshop.

Included Materials

Customized Training

At times, your engineering team may require unique training to meet the needs of your specific projects.  Sutherland HDL can customize our standard workshops to meet those needs, when presented as a private onsite or online workshop.  request info

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