About Sutherland HDL, Inc. and Stuart Sutherland
Sutherland HDL provides expert Verilog and SystemVerilog training services, and short-term design and verification consulting services.
Sutherland HDL was founded in 1992, and is located near Portland Oregon, USA. Our training workshops help engineers become true Verilog and SystemVerilog wizards! These workshops are developed and presented by engineering experts with many years of experience in design and verification. Sutherland HDL has trained thousands of engineers throughout the United States, and in Canada, England, Germany, Japan, Malaysia, and Hong Kong.
- "The class materials are excellent. The instructor was able to convey heavy technical material and still make the class fun and full of energy."
- "For sure the best course I've ever had!"
- "The instructor was clearly an expert and extremely good at presenting the material."
- "Excellent class. Definitely worth the time. The instructor kept my interest the entire time."
- "Best workshop I've attended. Very informative and insightful."
Stuart Sutherland, founder of Sutherland HDL, is a recognized Verilog and SystemVerilog expert, with more than 25 years of experience with Verilog and SystemVerilog. He is an active member of the IEEE Verilog and SystemVerilog standards group. He is also been a technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals, and has authored several popular books and conference papers on Verilog and SystemVerilog. Stuart holds a Bachelor's Degree in Computer Science with an emphasis in Electronic Engineering Technology (Weber State University and Franklin Pierce University) and a Master's Degree in Education with an emphasis on eLearning online course development (Northcentral University).
A few highlights of Mr. Sutherland's career include:
- Developer of comprehensive training courses on Verilog, SystemVerilog, UVM, and the PLI, VPI and DPI programming interfaces.
- Member of the IEEE 1364 Verilog standards group since its inception in 1993.
- Member of the IEEE 1800 SystemVerilog standards group since its inception in 2001.
- Chaired the PLI task force within the IEEE 1364 standards group.
- Editor of every version of the IEEE Verilog 1364 and SystemVerilog 1800 Language Reference Manuals.
- Author or co-author of numerous papers on Verilog and SystemVerilog.
- Receiver of several "Best Paper" and "Best Presenter" awards at technical conferences.