form_workshop-register

Currently scheduled open-enrollment eTutored online workshops

(Red fields must be filled in.)

Select a Workshop (check one or more)

SystemVerilog Object Oriented Verification
September 11-15, 2017
$2,000 before discounts* Mastering SystemVerilog UVM
September 18-21, 2017
$1,500 before discounts* Verilog/SystemVerilog for Design and Synthesis
October 2-6, 2017
$2,000 before discounts* SystemVerilog Assertions for Design and Verification Engineers
October 9-11, 2017
$1,000 before discounts*

* Sutherland HDL will contact you within 3 business days for payment information. Any discounts will be applied at that time.

Name

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Phone Number

Area code and number (e.g. 555-555-5555) or
country code and number (e.g. +1-555-555-555)

Company

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Shipping Address

Comments or Questions:

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A Sutherland HDL representative will contact you within 3 business days to confirm you registration and collect your payment information. Credit Cards are not charged until 7 days before the workshop date.