6.0 Module Port Declarations

7.0 Data Type Declarations

delay (optional) may only be specified on net data types. The syntax is the same as primitive delays.

decay_time (optional) specifies the amount of time a trireg net will store a charge after all drivers turn-off, before decaying to logic X. The syntax is (rise_delay, fall_delay, decay_time). The default decay is infinite.

7.1 Register Data Types

A module may be instantiated using port order or port names.

	Port order instantiation lists signal connections in the same order as the port list in the module definition. Unconnected ports are designated by two commas with no signal listed.
	Port name instantiation lists the port name and signal connected to it, in any order.

instance_name (required) is used to make multiple instances of the same module unique from one another.

instance_array_range (optional) instantiates multiple modules, each instance connected to separate bits of a vector.

	The range is specified as [lhi:rhi] (left-hand-index to right-hand-index).
	If the bit width of a module port in the array is the same as the width of the signal connected to it, the full signal is connected to each instance of the module port.
	If the bit width of a module port is different than the width of the signal connected to it, each module port instance is connected to a part select of the signal, with the right-most instance index connected to the right-most part of the vector, and progressing towards the left.
	There must be the correct number of bits in each signal to connect to all instances (the signal size and port size must be multiples).

Parameters in a module may be redefined for each instance.

	Explicit redefinition uses a defparam statement with the parameter's hierarchical name.
	Implicit redefinition uses the # token as part of the module instantiation. Parameters must be redefined in the same order they are declared within the module.

module reg4 (q, d, clock);
  output [3:0] q;
  input [3:0] d;
  input clock;
  wire [3:0] q, d;
  wire clock;
  
  //port order connection,2nd port not connected
  dff u1 (q[0], , d[0], clock);

  //port name connection, qb not connected
  dff u2 (.clk(clock),.q(q[1]),.data(d[1]));

  //explicit parameter redefine
  dff u3 (q[2], ,d[2], clock);
  defparam u3.delay = 3.2;

  //implicit parameter redefine
  dff #(2) u4 (q[3], , d[3], clock);
endmodule

module dff (q, qb, data, clk);
  output q, qb;
  input data, clk;

  parameter delay = 1; //default delay parameter

  dff_udp #(delay) (q, data, clk);
  not (qb, q);
endmodule

module tribuf64bit (out, in, enable);
  output [63:0] out;
  input [63:0] in;
  input enable;
  wire [63:0] out, in;
  wire enable;
  
  //array of 8 8-bit tri-state buffers; each instance is connected
  //to 8-bit part selects of the 64-bit vectors; The scalar
  //enable line is connected to all instances

  tribuf8bit i[7:0] (out, in, enable);

endmodule

module tribuf8bit (out, in, enable);
  output [7:0] y;
  input [7:0] a;
  input en;
  wire [7:0] y, a;
  wire en;
  
  //array of 8 Verilog tri-state primitives each bit of the
  //vectors is connected to a different primitive instance
  bufif1 u[7:0] (y, a, en);
endmodule

strength (optional) is specified as (strength1, strength0) or (strength0, strength1) Refer to Logic Strengths for strength keywords.

Only gate primitives may have drive strength specified. Switch primitives pass the input strength to the output. Resistive switches reduce the strength as it passes through.

instance_name (optional) may used to reference specific primitives in debugging tools, schematics, etc.

instance_array_range (optional) instantiates multiple primitives, each instance connected to separate bits of a vector.

	The range is specified as [lhi:rhi] (left-hand-index to right-hand-index).
	The primitive instances are connected with the right-most instance index connected to the right-most bit of each vector, and progressing towards the left.
	Vector signals must be the same size as the array.
	Scalar signals are connected to all instances in the array.

type_of_block @(sensitivity_list)
  statement_group: group_name
  local_variable_declarations
  timing_control procedural_statements
end_of_statement_group
  

type_of_block is either initial or always

	initial procedural blocks process statements one time.
	always procedural blocks process statements repeatedly.

sensitivity_list (optional) is an event timing control that controls when all statements in the procedural block will start to be evaluated. The sensitivity list is used to model combinational and sequential logic behavior.

statement_group--end_of_statement_group is used to group two or more procedural statements together and control the execution order.

	begin--end groups two or more statements together sequentially, so that statements are evaluated in the order they are listed. Each timing control is relative to the previous statement.
	fork--join groups two or more statements together in parallel, so that all statements are evaluated concurrently. Each timing control is absolute to when the group started.

group_name (optional) creates a local scope in a statement group. Named groups may have local variables, and may be disabled with the disable keyword.

initial
  fork
    bus = 16'h0000;
    #10 bus = 16'hC5A5;
    #20 bus = 16'hFFAA;
  join
    

always @(a or b or ci)
  begin
    sum = a + b + ci;
  end
    

always @(posedge clk)
  q <= data; 

#delay

Delays execution for a specific amount of time. The delay may be a literal number, a variable, or an expression.

@(edge signal or edge signal or ... )

Delays execution until there is a logic transition on a signal.

	edge (optional) maybe either posedge or negedge. If no edge is specified, then any logic transition is used.
	or is used to specify events on any of several signals.
	signal may be scalar or vector, and any data type.

wait (expression)

Delays execution until the expression evaluates as true.

if (expression)
   statement or statement_group

Executes the next statement or statement group if expression evaluates as true.

if (expression)
   statement or statement_group
else
   statement or statement_group

Executes the first statement or statement group if expression evaluates as true. Executes the second statement or statement group if expression evaluates as false or unknown.

case (net_or_register_or_literal)
   case_match1: statement or statement_group
   case_match2,
   case_match3: statement or statement_group
   default: statement or statement_group
endcase

Compares the net, register or literal value to each case and executes the statement or statement group associated with the first matching case. Executes the default if none of the cases match (a default case is optional).

casez (net_or_register_or_literal)

Special version of the case statement which uses a Z logic value to represent don't-care bits.

casex (net_or_register_or_literal)

Special version of the case statement which uses Z or X logic values to represent don't-care bits.

forever statement or statement_group

An infinite loop that continuously executes the statement or statement group.

repeat (number) statement or statement_group

A loop that executes the statement or statement group a set number of times. Number may be an integer, a variable, or an expression (a variable or expression is only evaluated when the loop is first entered).

while (expression) statement or statement_group

A loop that executes a statement or statement group as long as an expression evaluates as true.

for (initial_assignment; expression; step_assignment) statement or statement_group

	Executes initial_assignment once when the loop starts.
	Executes the statement or statement group as long as the expression evaluates as true.
	Executes the step_assignment at the end of each pass through the loop.

disable group_name;

Discontinues execution of a named group of statements. Simulation of that group jumps to the end of the group without executing any scheduled events.

//A 50 ns clock oscillator that starts after 1000 time units
initial
  begin
    clk = 0;
    #1000 forever #25 clk = ~clk;
  end
    

//sensitivity list models sequential logic
always @(posedge clk)
  begin
    //Non-blocking assignments avoid race conditions in the byte swap
    word[15:8]<= word[7:0];
    word[7:0] <= word[15:8];
  end
    

//sensitivity list models combinational logic
always @(a or b or sel)
  if (sel==0) y = a + b;
  else y = a * b;
    

//sensitivity list models sequential logic
always @(posedge clk)
  begin
    casez (opcode) //casez makes Z a don't care
      //? in literal integer is same as Z
      2'b1??: alu_out = accum;
      2'b000: while (bloc_xfer) //loop until false
                repeat (5) @(posedge clk)
                  begin //loop 5 clock cycles
                    RAM[address] = data_bus;
                    address = address + 1;
                  end
      3'b011: begin : load //named group
                integer i; //local variable
                for (i=0; i<=255; i=i+1)
                  @(negedge clk)
                    data_bus = RAM[i];
              end
      default: $display("illegal opcode");
    endcase
  end
    

Operators perform an operation on one or two operands:

Unary expressions

operator operand

Binary expressions

operand operator operand

The operands may be either net or register data types. Operands may be scalar, vector, or bit selects of a vector. Operators which return a true/false result will return a 1-bit value where 1 is true, 0 is false, and X is indeterminate.